The present invention relates to a semiconductor device and more particularly to a semiconductor device and a method of manufacturing the same, in which floating body memories are formed in vertical pillars.
Research has been conducted for a semiconductor device that can perform desired operations stably as future developments lead to higher integration, greater operation speeds, and reduced power consumption of the semiconductor device. As a result of the research, a floating body memory, in which a plurality of carriers are charged up in a floating body without using a capacitor to change the threshold voltage (Vt) of a transistor, making it possible to write and read data has been disclosed.
In the floating body memory described above, if hot carriers are generated when a high positive voltage potential is  applied to a drain, electron-hole pairs are produced as a result of impact ionization by the hot carriers. When the electron-hole pairs are produced due to impact ionization, holes accumulate in a silicon layer being a floating body and electrons are discharged to the drain by the high voltage applied to the drain. Accordingly, the threshold voltage (Vt) of a transistor is reduced as the holes accumulate in the silicon substrate, and when applying a voltage to the drain, a large amount of current can flow, by which the transistor serves as a memory. For example, in the floating body memory, “0” indicates a state in which holes are not accumulated and the threshold voltage is high, and similarly “1” indicates the state in which holes are accumulated and the threshold voltage is low. In the floating body memory, an erasing operation executed by applying a forward bias to the PN junction between a source and the silicon substrate and thereby discharging the accumulated holes to the outside.
In the floating body memory discussed above no capacitor is formed, and therefore a capacitor forming process and a capacitor forming area are not required. Accordingly, when compared to a typical dynamic random access memory (DRAM), the floating body memory is advantageous in that the number of processes required to realize the floating body memory is decreased and density is increased.
The floating body memory is realized on a silicon on  insulator (SOI) wafer having a stacked structure that includes a silicon substrate, a buried oxide layer, and a silicon layer. The floating body memory is not realized on a single crystal silicon wafer made of bulk silicon.
However, the SOI wafer is highly expensive and using the SOI wafer is difficult, and as such the manufacturing costs are great when realizing the floating body memory with the SOI wafer as discussed above. Further, the buried oxide layer is formed through an oxygen ion implantation process and an annealing process in the SOI wafer, which can result in defects in silicon due to the oxygen ion implantation process. Therefore, the use of the SOI wafer is likely to deteriorate the characteristics of a semiconductor device.